Novel Synchronous Counters Using Flip Flops for Low Power Applications

In this paper, a flip flop performance that combines logic operations with conventional flip flop behaviour is presented. The proposed logic flip flop will minimise implementation space, power consumption, and latency. Due to the rapid increase in power density in integrated circuits, area and power dissipation have become virtual design metrics. The simplest building blocks for storing information are latches and flip flops. In the dual dynamic flip flop is a well-known construction that loses less energy. The MOSFET approach is used in this research to design a dual dynamic flip flop that uses less standby power but has higher threshold voltages. A new dual dynamic flip flop with little area and power is called the DDFF. Because, there are fewer transistors in the suggested architecture and a larger pre charge node capacitance, it dissipates less power. The enhancements show that the suggested architecture is appropriate for high-performance digital circuits where space and power dissipation are critical factors. In comparison to typical flip flops, the suggested flip flop reduces power dissipation by 50% to 60% and area by up to 48%. A signal that uses the suggested flip flop and has low power dissipation is called a shift register. The proposed design in implement in Xilinx tool. The area and power consumption of the design is less when compared with the existing design.