The growing market of semiconductors needs low-power-consuming chips to be designed. SRAMs have long been a component of VLSI. SRAM power dissipation is a significant issue that has resulted in several innovations to reduce power dissipation. In this research paper, we intend to design a low-power 6 T SRAM using the CMOS technology and a 4 T SRAM using two high-value resistors (R = 1 k), and we compare their power at temperatures ranging from 20 °C to 120 °C. Due to the increased demand for SRAMs in SOC, maintaining the oxide layer thickness has become a difficult task by which speed and power consumption must be taken into consideration while designing. This paper gives a schematic diagram of 6 T SRAM and 4 T SRAM, as well as DC analysis and the transient response of 6 T SRAM and 4 T SRAM cells. The results suggest that a 6 T SRAM cell using 65 nm technology consumes less power than a 4 T SRAM cell. The Cadence Virtuoso design tool is used for creating schematic diagrams and comparing SRAM cell power efficiency with different temperatures. We have taken a voltage supply of 1.08 V given for the SRAM cells designed under 65 nm technology to get a better result.