The impending realization of scalable Quantum computers has led to active research in Post-Quantum Cryptography. Amongst various classes of Quantum-resistant cryptographic schemes, Lattice-based cryptography is emerging as one of the most viable replacements; five out of seven 3rd round finalists in the NIST Post-Quantum Cryptography competition are Lattice-based in their construction. This chapter surveys the practicality of deployment of some of these schemes as coprocessors for high-speed applications. The study of Post-Quantum Cryptography schemes as coprocessors on custom hardware platforms is imperative since they are much more computationally intensive, compared to their classical counterparts used today. Additionally they generally have much larger key sizes, requiring higher storage budgets as well. In this context the performance requirements of a cryptosystem, area, power and memory footprints, are bench-marked, along with side channel attack resistance (if provided). This chapter discusses Lattice-based cryptosystems implemented on configurable hardware (primarily Field Programmable Gate Arrays (FPGAs) and some Application-Specific ICs results), embedded processors for light-weight IoT end-node devices, Application-Specific Instruction Set Processors (ASIPs) and a few hardware software coprocessing designs. Most of these reported results are manually optimised with a few high level synthesis optimisations. The chapter concludes by identifying some research gaps and an outlook for the future.