Recent years have seen a rising popularity of FPGA-based compute acceleration as well as significant advances in the compilation tools that aim to make FPGAs accessible to software programmers. Modern FPGA-specific compilers, especially in the form of high-level synthesis (HLS) tools, have been increasingly used to automatically generate optimized accelerators from software programs. In this chapter the authors begin by surveying contemporary HLS compilers, followed by an anatomy of factors affecting the throughput of a custom accelerator, i.e., parallelism, utilization, and frequency. The authors then discuss four major categories of optimization techniques that are commonly used in HLS to generate high-performance accelerators, including pipelining, parallelization, memory customization, and data type customization. For each category, the authors survey a subset of the optimization techniques found in the recent literature and commercial tools. In the end, the authors use a binarized neural network as a case study to demonstrate the usage and benefits of these techniques.