This paper discusses the analysis of Negative Capacitance based junctionless Nanowire FeFET for memory cell applications. The persistent scaling of computer capacity is necessary to handle the data's rapidly rising volume and complexity. Dimensional scalability of field effect transistors (FETs) has reached the boltzmann tyranny limit because of transistors’ inability to handle the power dissipation. The new nanotechnologies have ability to replace the currently used CMOS and other technologies in energy-efficient computer devices. For information systems, negative capacitance based junctionless nanowire ferroelectric FETs are a potential candidate to continue improving power consumption. The NCFeFET analysis is carried out by evaluating drain current, transconductance, energy band, electric field, acceptor concentrations, and electric potential, conduction current density. Due to their energy, area efficiency and combined logic-memory functions, NCFeFETs, at the edge of semiconductor technology, are capable of meeting the requirements of integrated data computer applications. The proposed NCFeFET device has high ON current and small OFF current. The device exhibits a sub-threshold slope of 64.4 mV/dec, and the threshold voltage of 0.477 V. The proposed structure of NCFeFET is designed and simulated using the Silvaco TCAD tool. Proposed NCFeFET devices provides high-density and high-performance circuit applications and would act as a promising candidate for the scientific and research community working in this area.