Re-GNN: A New Model for Predicting Circuit Reliability Degradation

As semiconductor technology continues to develop, fragment integration levels are constantly increasing, principal to smaller and more complex electronic devices. However, concurrently, factors such as process variations and device aging are gradually revealing their significant impact on circuit reliability. These factors not only pose challenges in circuit design and production but also represent potential threats to the performance and lifespan of electronic devices. Traditional analysis methods are no longer practical in scenarios of increasing integration levels, leading to unacceptable performance losses. In contrast, process-variation and aging-aware Static Timing Analysis (STA) offer design engineers a way to accurately estimate statistical delay distributions and assess the impact of these factors. However, STA is both expensive and complex, relying on intensive Monte Carlo simulations and requiring access to confidential, physics-based circuit aging models to generate the necessary standard cell libraries. This paper introduces a novel application of Graph Neural Networks (GNN) for the precise estimation of process variations and device aging effects on circuit delay along any path. The proposed Re-GNN framework enables design engineers to perform reliability estimation more efficiently, eliminating the need for transistor models, standard cell libraries, or even STA. Extensive experiments demonstrate successful estimation of delay degradation for all paths in EPFL and ITC-99 benchmark tests. These findings present a fresh approach to address circuit reliability concerns, providing potential solutions to ensure the performance and reliability of electronic devices amid ongoing advancements in semiconductor technology.