Adders are vital in modern computing, especially in fields like AI and machine learning. Recent research combines parallel computing and VLSI design to develop advanced FPGA architectures. Nevertheless, the problem that has to be solved is that the adder’s space and power consumption grow in conjunction with the rise in the number of bits that are being added. Hence, there is a growing emphasis on designing adders that are not only area-efficient but also power-efficient, addressing the need for improved performance without compromising on energy consumption. A comprehensive survey of diverse adder architectures, including Ling, Han-Carlson, Weinberger, RCA, conventional CSLA, and SQRT CSLA, is carried out, which in turn helps to formulate a novel hybrid adder. Simulation and synthesis are executed utilizing Vivado 2019.1, while performance evaluation is performed with Cadence Genus tools across both 90 and 180 nm CMOS technologies. Results reveal that the hybrid adder outperforms existing designs, achieving specific improvements for area and power efficiency.