In this chapter a glimpse of the subject to testing combinational circuitCombinational circuit will be elaborated. It was not our intention to cover the complete subject of digital testing since it is out of the scope of this book. The idea is here, to prepare the reader for understanding the concepts of design for testabilityDesign for testability (DFT) which will be elaborated later. Having in mind, however, that our aspirations are toward testing of mixed-signal (or hybrid) circuits, the explanation given here will be rather helpful to deal with the problem as a whole. Electronic testing devices, testing procedures, and test signal generation for digital circuits differ significantly from analog circuit testing. Basically, the difference lies in the diversity of the signals that appear. Namely, with digital circuits, faulty operation is established in only one way. The signal at the measuring point should have the opposite value to the value it would have if the circuit were fault-free. Hence the test signal generation strategy. It should ensure that condition. When we say test, when testing digital circuits, we mean one digital wordDigital word, the bits of which determine the states of the input terminals. For example, for the gate of Fig.  7.1.6 , the input word contains three bits ABC. A maximum of eight tests can be compiled for this gate. In order to review the procedures for generating test signals (TSGTSG, from test signal generation) for digital circuits, we will first consider the basic principles of testing. Next, we will show the procedures for testing combinational circuits. Special attention will be paid to automatic test generation. Based on these considerations, the basic concepts of design for testability and self-testing will be presented in the next chapters. The presentations that follow are mainly based on existing textbooks or monographs (Zwoliński in Digital system design with VHDL. Pearsons, 2003 [1]; Roth in Computer logic, testing and verification. Pitman, London, 1980 [2]; Abramovici et al. in Digital system testing and testable design. Computer Science Press, New York, 1990 [3]; Rice in Computer-aided design, testing, and packaging. IEEE Computer Society Press, Piscataway, 1982 [4]; Bleeker and van den Eijnden in Boundary-scan test, a practical approach. Kluwer Academic Publishers, Dordrecht, 1993 [5]; Cortner in Digital test engineering. Wiley, New York, 1987 [6]; Wilkins in Testing digital circuits. Van Nostrand Reinhold (UK), UK, 1986 [7]; Liu in Testing and diagnosis of analog circuits and systems. Van Nostrand Reinhold, New York, 1991 [8]; Williams in VLSI testing. North-Holland, Amsterdam, 1986 [9]), standards (Williams in IEEE standard test access port and boundary-scan architecture. IEEE, New York, 1993 [10]; Williams in P1149.4 mixed-signal test bus standard. Working group meetings, minutes, and associate materials. IEEE, New York, 1995 [11]; Williams in Supplement to IEEE Std. 1149.1-1990, IEEE standard test access port and boundary-scan architecture. IEEE, New York, 1995 [12]; Williams in P1149.4 mixed-signal test bus. IEEE Standard Project. IEEE, New York, 1995 [13]; Williams in International technology roadmap for semiconductors. 2003 Edition modeling and simulation. https://www.semiconductors.org/resources/2003-international-technology-roadmap-for-semiconductors-itrs/ , 2003 [14]; Williams in Testing of electronics. https://www.jtag.com/testing-of-electronics-tutorial-jtag/ , 2023 [15]), as well as on original works (Roth in Diagnosis of automata failures: a calculus and a method. IBM J 278–291, 1966 [16]; Cha et al. in 9-V Algorithm for test pattern generation of combinational digital circuits. IEEE Trans Comput C 27(3):193–200, 1978 [17]; Goel in An implicit enumeration algorithm to generate tests for combinational logic circuits. IEEE Trans Comput C 30(3):215–221, 1981 [18]; Fujiwara and Shimono in On the acceleration of test generation algorithms. IEEE Trans Comput C 32(12):1137–1144, 1983 [19]).

7.5 Testing Combinational Logic

章节
发表日期：

2025年

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Vančo B. Litovski

摘要

In this chapter a glimpse of the subject to testing combinational circuitCombinational circuit will be elaborated. It was not our intention to cover the complete subject of digital testing since it is out of the scope of this book. The idea is here, to prepare the reader for understanding the concepts of design for testabilityDesign for testability (DFT) which will be elaborated later. Having in mind, however, that our aspirations are toward testing of mixed-signal (or hybrid) circuits, the explanation given here will be rather helpful to deal with the problem as a whole. Electronic testing devices, testing procedures, and test signal generation for digital circuits differ significantly from analog circuit testing. Basically, the difference lies in the diversity of the signals that appear. Namely, with digital circuits, faulty operation is established in only one way. The signal at the measuring point should have the opposite value to the value it would have if the circuit were fault-free. Hence the test signal generation strategy. It should ensure that condition. When we say test, when testing digital circuits, we mean one digital wordDigital word, the bits of which determine the states of the input terminals. For example, for the gate of Fig. 7.1.6 , the input word contains three bits ABC. A maximum of eight tests can be compiled for this gate. In order to review the procedures for generating test signals (TSGTSG, from test signal generation) for digital circuits, we will first consider the basic principles of testing. Next, we will show the procedures for testing combinational circuits. Special attention will be paid to automatic test generation. Based on these considerations, the basic concepts of design for testability and self-testing will be presented in the next chapters. The presentations that follow are mainly based on existing textbooks or monographs (Zwoliński in Digital system design with VHDL. Pearsons, 2003 [1]; Roth in Computer logic, testing and verification. Pitman, London, 1980 [2]; Abramovici et al. in Digital system testing and testable design. Computer Science Press, New York, 1990 [3]; Rice in Computer-aided design, testing, and packaging. IEEE Computer Society Press, Piscataway, 1982 [4]; Bleeker and van den Eijnden in Boundary-scan test, a practical approach. Kluwer Academic Publishers, Dordrecht, 1993 [5]; Cortner in Digital test engineering. Wiley, New York, 1987 [6]; Wilkins in Testing digital circuits. Van Nostrand Reinhold (UK), UK, 1986 [7]; Liu in Testing and diagnosis of analog circuits and systems. Van Nostrand Reinhold, New York, 1991 [8]; Williams in VLSI testing. North-Holland, Amsterdam, 1986 [9]), standards (Williams in IEEE standard test access port and boundary-scan architecture. IEEE, New York, 1993 [10]; Williams in P1149.4 mixed-signal test bus standard. Working group meetings, minutes, and associate materials. IEEE, New York, 1995 [11]; Williams in Supplement to IEEE Std. 1149.1-1990, IEEE standard test access port and boundary-scan architecture. IEEE, New York, 1995 [12]; Williams in P1149.4 mixed-signal test bus. IEEE Standard Project. IEEE, New York, 1995 [13]; Williams in International technology roadmap for semiconductors. 2003 Edition modeling and simulation. https://www.semiconductors.org/resources/2003-international-technology-roadmap-for-semiconductors-itrs/ , 2003 [14]; Williams in Testing of electronics. https://www.jtag.com/testing-of-electronics-tutorial-jtag/ , 2023 [15]), as well as on original works (Roth in Diagnosis of automata failures: a calculus and a method. IBM J 278–291, 1966 [16]; Cha et al. in 9-V Algorithm for test pattern generation of combinational digital circuits. IEEE Trans Comput C 27(3):193–200, 1978 [17]; Goel in An implicit enumeration algorithm to generate tests for combinational logic circuits. IEEE Trans Comput C 30(3):215–221, 1981 [18]; Fujiwara and Shimono in On the acceleration of test generation algorithms. IEEE Trans Comput C 32(12):1137–1144, 1983 [19]).