A procedure is described in this chapter that allows concurrent fault simulation of linear electronic circuits. It is based on the Modified Nodal AnalysisModified Nodal Analysis (MNA) which is extensively used for circuit equation formulation. The concept of stampsStamp is followed and proper stamps are given for all linear fault-free and faulty circuit elements including two- and four-terminal ones. A special feature of the method is its ability to model catastrophic faultsCatastrophic fault. The method insists for the LU factorizationLU factorization of the circuit matrix to be implemented in order to reach its effectiveness. Examples are given performing fault simulation in DC regime and in time domain simulation. Finally, a short study of the efficiency of the method is given showing its advantages. Special warning is given for fault simulation of linear circuit being created as linearized models of nonlinear ones since change in some circuit elements may affect the quiescent operating point of the original nonlinear circuit and so making the fault simulation inaccurate.