Sub-threshold Model of NMOS for Low-Power Application

The work in this paper investigates the optimization of N-type Metal Oxide Semiconductor Field Effect Transistor (NMOS FET) device through a systematic exploration of thickness variations using Silvaco TCAD tool. The study is motivated to enhance device performance while varying physical dimensions of MOS structures. The experimental approach involves the simulation and analysis of two NMOS devices under varying thickness conditions according to standard mathematical relations in between physical parameters and transfer characteristics. The proposed structure significantly improves the drain current \({I}_{D}\) (from 0.46 to 1.86 mA), linear gain β (from 1.27835 × 10–5 to 2.7653 × 10–5) and the sub-threshold voltage \({V}_{\text{TH}}\) (from 0.259 to 0.065 V). These enhancements underscore the crucial role of layer thickness optimization, in enhancing NMOS transistor functionality.