Prefetching Mechanism for Distributed Cache Architecture: Trends and Challenges

In recent years, the demand for more computing power has exponentially grown, leading to new processor architectures being developed to meet these demands. Among these, tiled chip multicore processors (TCMP) have been significantly gaining attention due to their scalability, power efficiency, and performance. A detailed survey of various prefetching mechanisms used in multicore processors and TCMP is provided in this paper. Designed to optimize prefetching, these mechanisms take into account the specific layout and communication patterns of the tiled architecture, aim to reduce inter-tile communication overhead and improve local cache hit rates. The role of the on-chip network, crucial in facilitating communication between tiles, is also a focus of discussion. This paper also highlights the necessity of efficient resource utilization and communication mechanisms. Two case study details are provided that incorporate TCMP architecture. A few evaluation metrics like cache hit time, IPC, and memory access time are discussed which are crucial for assessing the impact of prefetching on system performance and efficiency.