Integrated Circuit (IC) design is driven by the ever-increasing need to improve the speed, reduce the area occupied on the chip, and reduce power consumption. The Finite Impulse Response (FIR) filters most find its applications in the design of ICs and have diverse applications. It becomes vital to control the speed of the circuit, power consumption, and area of the FIR filters as they are an integral part of many chips. The design of adder blocks, multiplier blocks, and delay elements in the FIR filter must be done to achieve high performance for the overall filter design. This research paper primarily focuses on the design of FIR filters that consume low power and have high speed using hybrid adders and multipliers. The proposed adder consists of the modified Carry Select Adders (CSA) architecture. Different types of multiplier architectures, such as Vedic, Wallace tree, and Array multiplier architecture are designed in combination with proposed hybrid adders and analyzed in terms of performance. The FIR filter is designed using a proposed hybrid adder and multiplier, and its performance is compared to that of the conventional architecture of the FIR filter design. To further increase the performance parameters of the designed FIR filter, low-power techniques such as data-driven clock gating are added into the modified FIR filter design. The modified architecture of the FIR filter designed using the proposed hybrid adder, hybrid multiplier, and data-driven clock gating is simulated in the Xilinx Vivado tool, its synthesized design is obtained, and its performance is measured in terms of parameters such as delay of the FIR filter, area occupied and consumption of the power. The proposed FIR filter for image processing was designed using the proposed hybrid adder and modified multiplier with the proposed adder, which showed a decrease of 53.57% in power consumption and a decrease of 54.79% in delay compared to the traditional FIR filter.