A 4-Input 8-Bit Comparator with Enhanced Binary Subtraction

The work introduces a novel approach for implementing a multi-input comparator with an enhanced 8-bit binary subtraction method to compare numbers effectively. By employing a full adder and utilizing the two's complement method with a carry-in (Cin) set to 1, the simulation involves adding the complement to achieve accurate results. The determination of the sign is based on the carry-out from the most significant bit, allowing for precise differentiation between positive and negative outcomes and aiding in overflow detection. Integrating an 8-bit adder significantly boosts the comparator's capability to handle larger numerical values. It facilitates parallel processing, addressing limitations in bit width and enhancing accuracy for both minimum and maximum value determinations. The analysis emphasizes the importance of Register-Transfer Level (RTL) components and provides insights into power aspects (0.241W on-chip power, 25.3 °C junction temperature, 1.4 °C/W effective thermal resistance), along with resource utilization metrics (2800 DSPs, 2060 BRAMs). The successful implementation of a 4-input 8-bit comparator demonstrates its potential across various digital applications. Despite overcoming subtraction challenges, future improvements may target faster operations, seamless integration into larger systems, and exploration of hardware aspects in Field-Programmable Gate Array (FPGA) or Application-Specific Integrated Circuit (ASIC) architectures. This research marks a significant advancement in enhancing the adaptability of digital computation in our evolving technological landscape.