Multipliers are one of the most widely and repetitively used blocks in many architectures. They are indispensable part of many arithmetic, signal processing and image processing applications. Conventional multipliers are usually slow. To reduce time complexity of multipliers various optimizations can be done in algorithm level, architectural level, or transistor level. By designing an efficient multiplier, all these processes can be improved exponentially in terms of latency and area. In this paper a multiplier is developed, using Vedic mathematics technique known as Urdhva Triyakbhyam. Generally, using a faster adder can improve the speed of a multiplier. Kogge-Stone-Adder is a parallel prefix adder, which is one of the fast adders. The benefit of the Kogge-Stone-Adder is that the delay doesn't noticeably rise as the adder's bit length increases, but area consumption will be high. So, in order to be efficient in terms of speed and area in proposed Vedic multiplier, modified Kogge-Stone-Adder is implemented as a submodule which will reduce area consumption by 66% when compared to multiplier with conventional kogge-stone-adder.