In the present paper, a 1-bit hybrid full adder (HFA) is designed and presented. The HFA essentially consists of two modules, a 2-input exclusive-OR/exclusive-NOR gate, and a 2:1 multiplexer. The proposed circuit has a performance upper edge in terms of metrics namely, power usage, transistor count, power-delay product (PDP), driving capability, and Power-delay-number of transistors product (PDNP). Simulative analysis using Tanner EDA tools for CMOS 45 nm technology node shows that in comparison to prior HFAs reported in the literature, the suggested circuit offers superior space demands and power. The proposed circuit is also analyzed with voltage scaling, and it is found that it offers the best performance at 1.2 V supply voltage. Compared to current one-bit hybrid full adder circuits, simulation findings demonstrate that the suggested design displays lower power consumption, lower PDP, requires fewer transistors, and lower PDNP value.

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Design and Analysis of a Novel High-Performance Adder Circuit for VLSI Applications

  • Himanshu Chaurasia,
  • Rajeevan Chandel

摘要

In the present paper, a 1-bit hybrid full adder (HFA) is designed and presented. The HFA essentially consists of two modules, a 2-input exclusive-OR/exclusive-NOR gate, and a 2:1 multiplexer. The proposed circuit has a performance upper edge in terms of metrics namely, power usage, transistor count, power-delay product (PDP), driving capability, and Power-delay-number of transistors product (PDNP). Simulative analysis using Tanner EDA tools for CMOS 45 nm technology node shows that in comparison to prior HFAs reported in the literature, the suggested circuit offers superior space demands and power. The proposed circuit is also analyzed with voltage scaling, and it is found that it offers the best performance at 1.2 V supply voltage. Compared to current one-bit hybrid full adder circuits, simulation findings demonstrate that the suggested design displays lower power consumption, lower PDP, requires fewer transistors, and lower PDNP value.