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This paper presents chip testing with compressed scan chains and use of SDC timing constraints. Using this compressor and decompressors, multiple number of test patterns can be applied to semiconductor chip for detecting greater number of faults. Earlier, a specific fault was detected by using patterns produced by ATPG for unwanted paths leading to more power consumption. However, this can be overcome using SDC (Synopsis Design Constraints). Experimental results obtained using full scan with compressor method and full scan with SDC are shown in this paper.

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Chip Testing Using Scan Chains with Compressors and SDC Timing Constraints

  • 会议论文

  • 发表日期：

    2025年

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  • Gude Shiva Kumar,
  • Sahil Narng,
  • Monika Mittal

摘要

This paper presents chip testing with compressed scan chains and use of SDC timing constraints. Using this compressor and decompressors, multiple number of test patterns can be applied to semiconductor chip for detecting greater number of faults. Earlier, a specific fault was detected by using patterns produced by ATPG for unwanted paths leading to more power consumption. However, this can be overcome using SDC (Synopsis Design Constraints). Experimental results obtained using full scan with compressor method and full scan with SDC are shown in this paper.