FPGA Implementation of Vector Reduction Algorithm for LFSR

When logic is tested on an IC, heat generated by power dissipation causes damage to the semiconductor. The IC’s life will be shortened due to this power waste. Therefore, to extend the life of an integrated circuit (IC), power dissipation must be reduced as much as feasible. Additionally, testing every potential test vector for proper IC operation is a limitation. To lower the power consumption during testing of a circuit under test (CUT), we have devised a bit-swapping linear feedback shift register (BS-LFSR). The BS-LFSR reorders the test vectors by swapping out a bit for its next closest neighbor bit. The vectors’ fault coverage capability is maintained, but the total Hamming distance (THD) is lowered to lower power consumption during the shifting operation.