An Efficient and Fast Hardware Implementation of Parallel BCH Decoder

The parallel BCH decoder contains many logical bit operations and is difficult to implement using traditional serial processors. This article proposes a parallel BCH decoder design method using hardware logic. On the one hand, parallel bit processing is achieved through Galois field adders, fixed factor multipliers and general multipliers; on the other hand, through the pipeline design and resource reuse of the processing units, efficient implementation of the entire module is achieved. Inverse-free Berlekamp-Massey algorithm and Chien search algorithm are used for solving the key equations during decoding process. The syndrome polynomials, error locator polynomials, roots of error locations are computed in a parallel manner using hardware. The proposed implementation can achieve a bandwidth more than 23 MB per second, which has the advantage of both low resource usage and high decoding efficiency. The module has been deployed on Zynq platform for the data security of NANDFLASH.