Implementation of FPGA-Based 3 Stage Pipelined RISC-V

RISC stands for Reduced Instruction Set Computing. RISC MIPS has been implemented but it is forced to carry out an instruction in one clock cycle. The baseline MIPS processor operates on 1.2 GHz, consuming 318.4 uW and an area of 558 cells. The DLX architecture has an observed power consumption of 0.325 W, but the DLX structure is not forced to work using “no-ops” and is operating at a 3 clock cycle latency in this system. The fundamental idea behind RISC architecture is to streamline and simplify the instructions that a computer's central processing unit (CPU) can execute. The system implemented describes an FPGA-based RISC processor that performs the three tasks of fetch, decode and execute; the system takes an input of a 32 bit instruction from a general-purpose register, performs a register-based logical operation via the ALU and stores the result in an address specified within the instruction itself. The system is made to show that if needed, a RISC processor could be synthesized on a FPGA.