Optimization Implementation of Combinational Arithmetic Units Using Reversible Logic

The process of computing that can be reversed involves computational models that possess. The theoretical properties of these models are intriguing, and they have appositeness in program reversal and bidirectional registering. The reason for this paper is to investigate how reversible ALU processing frameworks can be executed at the actual door level. Number-crunching tasks are a reason for the overwhelming majority registering skeleton, so a volunteered the plan of adder, subtractor, multiplexer, multiplier, comparator, and memory element, i.e., delay flip flop (D_FF) work toward a reversible circuit. The adder and subtractor circuit consist of DKG gate; multiplexer circuit consists of R gate; multiplier consists of toffoli, Peres and HNG gate; comparator consists of BJN gate; and D_FF consists of Feynman and Fredkin gate. Xilinx software was used in all designs, and VHDL text benches were simulated.