Novel Architecture of 16-Bit ALU Design Using PERES Gates
摘要
Reversible logic gates are an emerging approach for developing highly computationally efficient architectures. The reversible logic-based 16-bit ALU implementation using Peres Gates is proposed to develop a better ALU architecture in terms of delay, area, and power. In this paper, 16-bit ALU and its Boolean and logical operations using Peres Gate have been simulated and synthesized. This work has been simulated and synthesized using XILINX ISE 13.2 on the targeted FPGA Spartan 3E.