Performance Improvement Techniques for High-Speed Dynamic Latch Comparator at 45-nm Technology Node

This paper examines three improvements made to a dynamic bias latch type comparator at a 45-nm technology node: tail-enhancing latch, modifying latch, and three-tail architecture. Extensive simulations show that the time delay is significantly reduced. When operating at low voltage, this decrease ranges from a minimum of 36.67% to a high of 82.99%. Conversely, the findings show a drop at higher voltage levels that ranges from a minimum of 24.53% to a maximum of 59.99%. This illustrates the reduced time delay achieved by the modified dynamic bias latch type comparator. Fast and precise analog-to-digital conversion is essential for real-time data processing, and high-speed dynamic latch comparators are essential for the Internet of Things, edge computing, and autonomous systems. They guarantee safety and efficiency by improving network responsiveness in the Internet of Things applications, lowering latency in edge computing, and enabling split-second decision-making in autonomous systems.