Architectural Implementation of High-Performance AES-GCM for Network Security

The need for hardware security increases day to day, especially with the involvement of sharing confidential data across the Internet. Information leakage through different unauthorized attacks is quite common, and one common type of attack is the scan chain-based attacks. The proposed paper uses a high-performance AES-GCM core to enhance throughput, frequency, and security. The area scavenging Substitution Box (S-Box) is the heart of an AES design. The classic LUT-based S-Box requires the addition of ROM in its design causing an increase in the area and delay. To overcome these drawbacks, S-Boxes are constructed using Composite Field Arithmetic (CFA), which employs distinct irreducible polynomial equations with no intermediate state storage. To include the confidentiality and authenticity into the design for added security, the Galois Counter Mode (GCM) is integrated into the AES design along with dual key G-Hashing. The AES-GCM core offers confidentiality via the AES mode and integrity and authenticity via the GHASH function introduced by the GCM mode. To increase the throughput rate, data-independent encryption and decryption are used, and for increasing the AES-GCM working frequency, 16 parallel pipelined stages are introduced. Integrating Robust Secure Scan Flip-Flops (RSFF) into the design has improved the security by multi-folds without any compromise on the testability feature, thus being a great countermeasure against scan chain-based attacks.