A Novel Approach in Estimating Wirelength in VLSI Placement Using Machine Learning

This paper presents a comparison of several machine learning (ML) models, namely artificial neural network (ANN), support vector machine (SVM), and random forest (RF), for estimating the wirelength of a VLSI cell placement. ML techniques offer a significant speedup with good accuracy compared to conventional methods like the rectilinear Steiner minimum tree (RSMT). The ML models are trained and tested using features and labels obtained from various wirelength estimation methods, including the half-perimeter wirelength (HPWL), rectilinear minimum spanning tree (RMST), and net degree. The ISPD 2011 benchmark circuits, consisting of over 7 million nets, serve as the dataset. Based on the results, RF achieves a runtime improvement of over 48 times with only 2% accuracy loss as compared to the classical RSMT, thus providing the best trade-off between wirelength estimation and accuracy. When integrating RF into the simulated annealing (SA) cell placement algorithm, results show 6 times faster execution than RSMT for equal number of SA iterations. Thus, with a goal of fast and accurate wirelength estimation in VLSI placement, ML-based methods have proven to be feasible and very effective.