A Low Power Single Ended and Dual Port 8T SRAM with Robust Features

Cache memory is a class of memory which is of paramount importance in today’s world. Cache memory supports systems with high memory demands such as the emerging technologies of Artificial Intelligence and Machine Learning. Static Random Access Memory (SRAM) cell constitutes the basic building block of cache memory. To make cache memory faster and more efficient, a breakthrough SRAM cell architecture which would increment its performance is required. This paper proposes a novel single-ended, dual-port SRAM cell architecture consisting of 8 transistors with improved parameters of noise margins, access delay, power consumption with tolerance for temperature and voltage drop variation, etc. The performance of the proposed SRAM cell is then compared alongside three other SRAM cell models using the same technology node, supply voltage and identical simulation conditions. Transient analyses of the proposed SRAM cell reveal a read and write delay of 83 ps and 126 ps, respectively. Analysis of power consumption shows that the proposed SRAM cell consumes dynamic read and write power of 12.8 \(\upmu \) W and 10.4 nW, respectively, and a static power consumption of 0.932 \(\upmu \) W. It was also observed to have static read and hold noise margin of 133.5 mV each and a write margin of 400.6 mV. Supply voltage variation to emulate voltage drop variation reveals variation of hold, read and write margin. Further, temperature variations were simulated which showed that hold, read and write noise margins varied at the rate of 0.77 mV/ \(^{\circ }\) , 0.79 mV/ \(^{\circ }\) and 0.58 mV/ \(^{\circ }\) respectively.