Optimization and Implementation of a 32-Bit MIPS-Based Softcore Processor to Run Statistical Algorithms on FPGA

The study focuses on the design optimization of the 32-bit MIPS-based processor to make it eligible to execute the statistical algorithms with pipelined architecture. Symmetric Overloaded Minimal Instruction Set Architecture (SOMA) (Jungwirth et al. in SoutheastCon 2023, Orlando, FL, USA, pp. 53–59, 2023 [1]) instruction set architecture and 4-stage pipeline is incorporated in the design to make the processor efficient for the statistical algorithms’ execution. For this study, a processor is designed in Verilog HDL, tested on the NEXYS DDR 4 FPGA board using Xilinx Vivado 2020.2. The comparison between 32-bit single-cycle MIPS-based processor and 32-bit SOMA ISA and 4-stage pipeline processor showed significant improvement in reducing the number of clock cycles and use of the number of registers/memory. Therefore, the study also proves the SOMA ISA with 4-stage pipelined version outperforms FPGA with MIPS-based architecture in terms of time consumption and memory usage. Study also suggests that FPGAs are less costly hardware testing platforms for new designs in the field of computer architecture, digital design, and microprocessors.