A Flexible and Balanced Hardware Architecture of RSA Modulo Exponentiation on FPGA
摘要
RSA modulo exponentiation is a critical cryptographic primitive widely employed in various network protocols and security applications. However the modulo exponentiation is very computational intensive and resource cost even implement in hardware. In this paper, we present an RSA architecture that is flexible and well balanced on FPGA. The results show that modulo exponentiation in RSA-2048 decryption/signing requires 19.8 ms, utilizing only 10% of the Virtex-7 FPGA chip.