Decoders are an important module used in the memory controller. This paper introduces an approach to build a 2-to-4 line decoder using a combination of Pass Transistor Logic (PTL) and Transmission Gate Logic (TGL) with sleep logic (TGL-PTL with sleep logic) to reduce power consumption and area overhead. This approach is taken forward to implement the same using a standby logic that switches off the circuits not in use when one of the outputs is functional to get a minimum power dissipation. The proposed 2-to-4 decoder required 62.66% and 9.53% less power dissipation as compared to the conventional and TGL-PTL logic-based decoders. The delay of the proposed decoder circuit is better than the conventional decoder circuit. For the process variations analysis, 2000 Monte Carlo simulations show that the standard deviation on power dissipation is only 0.69 nW as compared to 9.26 nW and 1.72 nW for conventional and TGL-PTL logic-based decoder circuits.