In this paper, phase-frequency detector and charge pump circuits using current mode logic (CML) have been proposed for use in phase-locked loops (PLL). The primary advantages are lower voltage swings and consequently faster current switching. This reduces clock feedthrough and charge injection which in turn achieves low PLL reference spurs. The overall PLL system has been demonstrated via simulations. The PLL uses the proposed tri-state CML phase-frequency detector, CML charge pump, a second-order passive loop filter at the transistor level, an ideal 1-GHz voltage-controlled oscillator, and frequency divider. The reference frequency is 50 MHz. The circuits are designed in TSMC 65 nm process, and consume 0.81 mW from a 1.2-V power supply. In simulations, the PLL exhibits an in-band phase noise of −112dBc/Hz at a 100-kHz offset, a reference spur of −72.2 dBc, and a lock time of 2.6 µs.