A 0.1–4.71 GHz Integer-N CP-PLL-Based Low-Power Frequency Synthesizer for High-Speed Applications
摘要
The aim of this study was to develop a GHz frequency synthesizer with high speed and low power consumption. The performance of the synthesizer was assessed through Cadence Virtuoso simulations within the CMOS 180nm technology by utilizing components such as a phase frequency detector, a differential ring oscillator, a charge pump, a loop filter, a level shifter, and a divider. The simulations revealed that the synthesizer had a power consumption of 4.9 mW with a supply voltage of 1.8V and achieved a lock time of 3.41 \(\upmu \) s. It could generate frequencies between 0.1 GHz and 4.71 GHz, occupying a chip area of 0.013 \({\text {mm}}^2\) . The proposed synthesizer exhibits a phase noise of –142.54 dBc/Hz at an output frequency of 4 GHz. This synthesizer achieves a Figure of Merit (FoM) of –174.49 dB. The synthesizer has potential applications in devices such as radio receivers, televisions, mobile phones, satellite receivers, and GPS systems.