The proposed work provides a characterization of multi- \(V_t\) CMOS transistors available in UMC 65 nm, 40 nm, and 28 nm technologies. The simulated \(I_D\) - \(V_{DS}\) characteristics of such transistors are estimated and trends are shown. Through a set of simulations, it has been observed that transconductance ( \(g_m\) ) hardly changes with the scaling of technology. The output conductance is linear in UMC 28 nm and 65 nm technology for LVT transistors and has low output conductance. The selective choice of multithreshold transistors enhances circuit performance. A single-ended inverter-based comparator designed using multithreshold transistors in UMC 65 nm CMOS technology and Cadence Virtuoso environment has been used for simulation studies. The simulation results demonstrate a maximum input offset of 25 \(\upmu \) V approximately over the full input signal range, thus achieving an 18-bit resolution.