Design of Ternary Combinational Circuits

‘Smart Agricultural’ practices are fueled by developments in IoT, VLSI, FPGA or similar approaches. However, present-day computational resources rely on binary logic (0s and 1s). Research shows that ternary logic (0s, 1s and 2s) has the potential to increase computational capabilities of present-day resources, hence the authors have designed and implemented ternary combinatorial circuits, using standard binary simulators such as LT Spice, Xilinx ISE 14.6 Design Suite and VHDL language. Ternary inverter gates, ternary universal logic gates and ternary half adder have been simulated. The simulation outputs have successfully matched with theoretical values. The following paper shall serve as the basis and inspiration for implementing further enhanced ternary circuits, which, in turn, will revolutionize the attempt to establish ‘smart agriculture’.