Principle of Embedded AI Chips

This chapter introduces the first component to implement embedded AI, the principle of the embedded AI chip. These chips can be streamlined versions of GPUs, TPUs, or ASICs and FPGAs designed for specific purposes. When needed, they will be integrated into embedded SoC chips. These chips adopt a parallel computing architecture and introduce concepts such as systolic arrays and multi-level caches to optimize data flow and minimize energy consumption by reducing memory access time during calculations. Multiple data flow strategies optimize data reuse and locality through innovative architectural approaches to reduce overall computing load and power requirements. This chapter also introduces the application of sparse matrix techniques that help compress data and speed up processing time.