The Development of a Communication System by a High Productivity, Low Power Consumption, and Memory-Based Architecture, Incorporating an FFT Processor

Elevated quantities configurable fast Fourier transform (FFT) processor has been developed for the purpose of facilitating the operations of 4G, wireless local area network, and forthcoming 5G technologies. Here processor in question allows for the execution of 16- to 4096-point FFTs and 12- to 2400-point discrete Fourier transforms (DFTs). In order to strike a balance among performance and cost, a memory-based architecture featuring 16 data parallel routes has been selected. Various improvements are available to design a high-performance central processing unit (CPU) that is optimized for hardware efficiency. The proposal suggests the utilization of a reconfigurable butterfly unit to facilitate computation. This unit is designed to perform 8 radix-2 computations in parallel, four radix-3/4 computations in similar, 2 radix-5/8 computations in corresponding, and one radix-16 computation within a single clock cycle. The primary objective of this design is to optimize the utilization of the hardware resource by maximizing its reuse. Different methods are employed to change and compare twiddle factor multipliers. Subsequently, an altered coordinate’s revolving digital computer system is utilized to decrease hardware expenses, whereas simultaneously facilitating the execution of both fast Fourier transforms (FFTs) and discrete Fourier transforms (DFTs). A proposed data access strategy that is optimized for conflict-free operations is also introduced, with the capability to accommodate numerous butterflies at various radices.