Implementation of a Density-Optimized High-Throughput and Efficient Built-In Self-Test (BIST) System Using Multiple Instruction Stream Computing (MISC) Architecture

The increasing intricacy of integrated systems and circuits has resulted in a heightened emphasis on the expense of testing. The significance of design-for-testability (DFT) is increasing, and it is emerging as a prominent focus in the advancement of the integrated circuit (IC) test sector. The utilization of Built-In Self-Test (BIST) is becoming more prevalent as a viable strategy for cost reduction in the field of testing. BIST is a methodological approach for DFT whereby the process of testing, including test preparation and test application, is carried out using embedded hardware functionalities. The integration of circuits into a system has the potential to render external test equipment unnecessary and enable the testing of devices post-integration. The BIST technique exploits a Pseudorandom Pattern Generator (PRPG) to generate test patterns with random characteristics, which are subsequently applied to the test circuit. In traditional BIST architectures, the utilization of the linear feedback shift register (LFSR) is prevalent in both the test pattern generators. However, a notable limitation of these techniques is the generation of pseudorandom patterns through the LFSR, resulting in a substantial increase in switching activities within the Circuit under Test (CUT). Consequently, this elevated switching activity may give rise to excessive power dissipation. In addition, these actions have the potential to inflict harm against the circuitry, resulting in less product output and a shortened operational lifespan. Moreover, it is typically necessary for the Linear Feedback Shift Register (LFSR) to produce pseudorandom progression of considerable length so as to attain the desired fault coverage with nanometer-scale technology.