Efficient VLSI Implementation of Image Denoising Using Hybrid Median Filter

Filters are essential for eliminating different types of image noise, like salt and pepper, random noise, and Gaussian noise. Consequently, the hardware implementation of these filters, tailored for very large-scale integration (VLSI) applications, is critical for real-time usage. However, traditional hardware-based filters struggle to minimize look-up-table (LUT) usage, minimize delays, and power consumption. This study focuses on implementing a resilient hybrid median filter (HMF) using data comparator (DC) to address these challenges. Initially, a data comparator based on multiplexer selection logic is employed to distinguish between high and low values in a pair of numbers. Subsequently, this data comparator is applied multiple times to combinations of nine pixels, determining the median value from this set. From the result, it indicates that the proposed resilient hybrid median filter outperforms than existing approaches. It excels by means of noise reduction and hardware metrics such as LUT usage, delay, and power consumption.