Design and Implementation of 16-Bit Posit Arithmetic

Posit numbers, intended to replace IEEE floating point numbers, have become the focus of mathematical research due to recent developments. This format is guaranteed to provide more accurate results than a float model of the same size, but it is hardware to control time changes during the process. In this work, we present the architecture of various operations, including addition and multiplication. The test shows improvement up to 39.15% in the area for multiplier and 11% of the area for adder, respectively, compared to the literature. The reduction in power is up to 29.74% for the adder and 66% for the multiplier, the transition switching of transistors is reduced in comparison with the literature.