Design of Hybrid Tester for VLSI Testing by Using Scan Chain Masking and Cell Re-ordering in Fault Diagnosis

The term testing plays an important role in VLSI design technology; it ensures the necessity of diagnosis of faults or defects in the various design stages of VLSI or ASIC flow. The paper addresses the issues associated with scan chain diagnosis process for multiple faults in multiple chains. To minimize effect of these issues, presented a scan chain masking technique for multiple scan chains to identify the faulty scan cell and respective chain which contains the faulty cell. The proposed scan chain masking technique gives good results in multiple fault diagnosis in multiple chains as well as in single chain and it is efficient in terms of cost of design. It also focusses into design area consumed by the tester in scan-based DFT. To minimize the problem of larger area utilization, addressed latch-based scan cell design. Therefore, proposed work has been solved the issues of using latches in scan design and designed power, area efficient latch-oriented tester for scan-based testing.