Design and Performance Analysis of Power-Efficient Phase Frequency Detector for PLL Application in 90 nm Technology

In this paper, Using 90 nm CMOS technology, a phase- frequency detector (PFD) design is presented. The main purpose of circuit design is to lower the power dissipation with a voltage supply of 1.8 V. The PFD has a variety of application and the primary uses is in the current phased locked loop, where PFD serves as the main building block. A PFD (Phase Frequency Detector) is a circuit that calculates the disparity in phase and frequency among two signals and provides two outputs, UP and DOWN, which are indicated with the appropriate frequency and phase difference in a pair of input signals. The designed circuit shows a suitable result with 1.8 V voltage supply. The detection of Phase difference occurs only at rising of two clock signals. The total power dissipation of transistor design and D flip-flop design is 2.297 nW and 19.053 uW respectively, which is considerably low. In the IC design field, power dissipation is always an important factor. The lower the power dissipation, the longer service life of battery-powered electronics circuit.