Dynamic Voltage and Frequency Scaling Implementation for System-Level Power Reduction

In recent years, power reduction approaches have become the primary preoccupation of VLSI engineers. Effective system-level power reduction is required to support electronic devices that are portable and reliable. Dynamic voltage and frequency scaling (DVFS) is one technique for optimizing power at the system level. The ability to vary the voltage and frequency allows for a significant reduction in energy without having a noticeable impact on the throughput. By making use of a workload predictor that monitors the rate of change of input data, suitable voltage and frequency values are selected and applied as discrete values during the run time. The proposed DVFS technique was implemented in Cadence Virtuoso in 45 nm technology. This technique on simulation proved to be successful in dissipating lower energy. The topology involves lower overhead and is scalable.