Design and Comparative Evaluation of 2:4 Decoder Utilizing Varied Static Design Paradigms

In the contemporary milieu, characterized by an ever-increasing appetite for mobile and energetically economical devices, the imperative for area-optimized, low-power, and high-velocity applications has assumed utmost precedence. Effectuating the miniaturization of a system entails the concerted endeavour of diminishing the dimensions of its foundational constituents. Considering these exigencies, this scholarly manuscript proffers a pair of propositions encapsulating 2:4 decoder designs, which are then subjected to meticulous scrutiny, juxtaposed against their conventional and existing counterparts as enshrined within scholarly discourse. The proposed decoders have been meticulously crafted utilizing 12 and 10 transistors, respectively. Through extensive simulation, conducted at a supply voltage of 0.8 V and employing two different technologies, namely the 22 nm and 16 nm, a comparative assessment of the simulation findings has been performed. The comprehensive examination unequivocally demonstrates that the suggested designs outshine their counterparts in terms of power consumption, propagation delay, average current, area efficiency, and overall energy efficiency.