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The paper presents a Parallel Digital Hardware architecture for Integrated Support Vector Machine Training and Classification. The architecture is designed with three layers of parallelism. As use case, 1000 data sets of diabetic patients are considered to classify diabetic and non-diabetic based on the Support Vector Machine (SVM) Algorithm. The design is synthesized using Cadence Genus with TSMC 180 nm technology. Design is much faster than software tools which are used to execute behavioral codes of AI/ML or faster than general-purpose CPU’s. The design takes 1024 \(\,\times \,\) 1024 clock cycles of period 7.147 ns which is in total 7.494 ms to train raw data sets which is attractively much better than software.

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Parallel Digital VLSI Architecture for Combined SVM Training and Classification

  • 会议论文

  • 发表日期：

    2025年

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  • Sidhant Priyadarshi,
  • Saroja V. Siddamal

摘要

The paper presents a Parallel Digital Hardware architecture for Integrated Support Vector Machine Training and Classification. The architecture is designed with three layers of parallelism. As use case, 1000 data sets of diabetic patients are considered to classify diabetic and non-diabetic based on the Support Vector Machine (SVM) Algorithm. The design is synthesized using Cadence Genus with TSMC 180 nm technology. Design is much faster than software tools which are used to execute behavioral codes of AI/ML or faster than general-purpose CPU’s. The design takes 1024 \(\,\times \,\) 1024 clock cycles of period 7.147 ns which is in total 7.494 ms to train raw data sets which is attractively much better than software.