Exploring the Efficiency of Vedic Mathematics on FPGA and ASIC: A Performance Analysis

Effective operation of arithmetic units is crucial for the intended functionality of systems, encompassing microprocessors and Digital Signal Processing (DSP) architectures. Invariably, hardware designed for such systems incorporates multipliers. This paper is centered on employing Vedic Mathematics Algorithms specifically for multiplication, aiming for power-efficient and compact designs. This research primarily delves into its application within the binary number systems commonly used in electronic devices. The study employs the Urdhva Tiryagbhyam (criss-cross) method for implementing four- and eight-bit Vedic multiplication. Performance analysis involves implementing these algorithms on a reconfigurable hardware platform. Additionally, traditional multiplication methodologies are constructed for comparison purposes. The findings suggest that Vedic algorithms exhibit faster operation, requiring fewer resources (measured in cell count) and reduced power consumption. Verilog HDL language, Xilinx ISE, and Quartus tools were utilized for these implementations. To measure various performance parameters, the paper used Cadence Innovus (90nm Technology) in conjunction with Xilinx ISE and Quartus tools.