Two-Layer Minimum Variance FIR Filter-Based DPLL Design

The digital phase-locked loop (DPLL) is a circuit used for phase synchronization in digital communication and control systems. The DPLL based on infinite impulse response (IIR) filters such as Kalman filters perform well, but performance degradation can occur in unexpected situations such as inaccuracy of initial value, model error, and disturbance. In this paper, we propose a two-layer minimum variance finite impulse state estimator to design a new digital phase-locked loop. To verify the superiority and robustness of the new DPLL, simulations were performed for comparison and analysis with the existing method in a situation in terms of inaccurate noise information.