The Design of High-Precision Σ-Δ Modulator with High FoMs

High-precision sigma delta analog-to-digital converter (ADC) is widely used in fields such as high-precision sensors, precision instruments, and high-quality audio at present. A third-order discrete-time Σ-Δ (sigma-delta) modulator with feedforward, single-loop structure using multi-bit quantizer implemented in a 180 nm bipolar-cmos-dmos (BCD) process is proposed which can be applied in high-precision ADC. Dependent on the chopping technique, flicker noise and input offset of the op-amp in the first integrator are attenuated while data weighted average (DWA) technology is used to improve nonlinear problems caused by multi bit feedback digital-to-analog convertor (DAC). The signal bandwidth is 5 kHz, the sampling frequency is 1.25 MHz, the supply voltage is 1.8 V, and the simulation results show that this modulator achieves a signal-to-noise distortion ratio (SNDR) of 115.22 dB and an effective number of bits (ENOB) of 18.85 bits, with a power consumption of 3.41 mW, and the Schreier’s figure of merit (FoMs) of 176.9 dB.