A High-Parallel High-Speed QC-LDPC Decoder Design Based on Second Minimum Value Estimation

QC-LDPC (Quasi-Cyclic LDPC) has gained widespread application in communication due to its superior error repair capability and suitability for high-throughput design. In the decoding algorithm, the Min-Sum Algorithm (MSA) significantly reduces the complexity of LDPC codes, making it easier to design hardware and requiring fewer resources. The estimation method of the second minimum value has garnered significant attention in order to streamline the MSA decoding algorithm. This paper draws inspiration from Eb/N0 and iteration counts to propose another form of the second minimum value estimation method. Compared with the current MSA decoding algorithm based on single minimum value, the new method can both improve error correction performance and consume more economical resources under QC-LDPC code (1944, 1620). Based on this method, a structurally designed high-parallel layered LDPC decoder is proposed. Implementation results show that, at a clock rate of 200 MHz, the decoder for the QC-LDPC (1944,1620) code was able to deliver a throughput of 3.77 Gb/s over 10 iterations.