As March C-based tests are all straightforward and have good fault coverage, March Algorithms are well-known for memory testing and are frequently used in contemporary memory Built-in self-test (BIST). Given that March methods are well known for assessing embedded RAMs, March C-algorithm is well known for locating all stuck-at fault (SAF) and coupling fault (CF), and has high usage in the industry. Every March algorithm possesses the complement symmetry because of testing the fault in two conditions i.e., logic 0 or logic 1. These two conditions are always considered to ensure that a fault is tested properly. By observing every March algorithm, a concept of complement is inherent that directly reduces the order of March algorithm from 10 to 5n. In this paper, a complementary symmetric approach of the March C-algorithm is proposed to test the memory along with the relevant hardware implementation. Because of the concept of complement symmetry, area wise storing requirement of the March algorithm is reduced due to the bit’s reduction, leading to an improved overall performance of the proposed algorithm in terms of Area, Timing and net, Cell count, and Power requirements. Additionally, this paper also proposes a possible hardware implementation of the newly proposed modified March C-algorithm by using counter and decoder. Simulation results are provided at the end of this paper which further highlight the improved performance of the proposed modified algorithm over the traditional March C-algorithm.