The Design and Analysis of Fast Fourier Transform Processor Using VLSI Technique

Power consumption, area, and timing affect the efficiency of the processor. There is an increasing demand for higher standards and improved performance in chip technology. The pursuit of better performance has become a prevailing objective among individuals and industries. As technology continues to advance, the standards for chip performance will undoubtedly rise, motivating researchers and manufacturers to strive for even greater achievements. The aim of this project is to study and analyse the performance requirements in terms of area, power consumption, and speed of a 16-point Radix-4 Fast Fourier Transform (FFT) processor. Furthermore, this project aims to create an efficient FFT processor chip. The simulation was carried out using Mentor Graphics QuestaSim, and the synthesis was done using Mentor Graphics Oasys-RTL. The project focused on the front-end design part, implementing the design with 130 nm CMOS process technology. The research methodology of the study implemented a modified flop-based design to facilitate timing optimization. The design has a low power consumption of 620.105 mW, a cell area of 1374521 µm2, and high overall performance. The design exhibits high speed and a smaller cell area. The performance of the proposed design has improved compared to the original design.