The Cyclic Redundancy Check (CRC) is a widely used error detection code in Ethernet, PCIe, and other transmission protocols. However, the current FPGA-based implementation solutions face issues with excessive resource utilization in high-performance scenarios. These problems are further compounded by the padding zeros problem and the need for programmability. To address these issues, we have proposed a solution that improves the utilization of memory, enhances accuracy, and optimizes logic operations during calculations. This is achieved by integrating stride-by-8 and stride-by-6 algorithms, which overcome the limitations of the stride-by-5 algorithms. To resolve the padding zero problems, we have suggested the use of the bit-wise reflection or bit reversal algorithm. Additionally, to enable programmability with minimal resource utilization, we have proposed the method of reprogramming by Hardware Internal Configuration Access Port (HWICAP). The proposed method will be synthesized and simulated using the Vivado Design Suite 2022.1 and realized on a Kintex-7 FPGA board.