Scholarlink

This paper presents a new architecture for an approximate unsigned multiplier, aiming to minimize both area utilization and power consumption while maintaining high accuracy. The architecture is divided into three regions: the least significant region (LSR), the approximate region, and the accurate region (most significant region). To improve hardware savings, the least-contributing to the final result, the LSR, is replaced with zeros. On the other hand, the approximate region utilizes two new approximate compressors, which are highly efficient 4:2 compressors introducing ‘+1’ and ‘−1’ errors. These compressors are carefully designed to offset each other’s error, thereby mitigating the overall error introduced by the approximation. Experimental results for 8-bit multipliers demonstrate that the proposed designs outperform the existing design in terms of power, achieving improvement of 15%. Furthermore, the proposed designs are evaluated using image processing and neural network applications.

错误：搜索内容不能为空，请输入英文关键词
错误：关键词超出字数限制，请精简
高级检索

Power Efficient Approximate Multiplier for Neural Network Applications

  • 会议论文

  • 发表日期：

    2025年

查看全文
  • Uppugunduru Anil Kumar,
  • Venkat Sai Arva,
  • Chamundeswari Kottur,
  • Abhishek Reddy Boppidi,
  • Abudhagir Umar Syed,
  • Sreehari Veeramachaneni,
  • Syed Ershad Ahmed

摘要

This paper presents a new architecture for an approximate unsigned multiplier, aiming to minimize both area utilization and power consumption while maintaining high accuracy. The architecture is divided into three regions: the least significant region (LSR), the approximate region, and the accurate region (most significant region). To improve hardware savings, the least-contributing to the final result, the LSR, is replaced with zeros. On the other hand, the approximate region utilizes two new approximate compressors, which are highly efficient 4:2 compressors introducing ‘+1’ and ‘−1’ errors. These compressors are carefully designed to offset each other’s error, thereby mitigating the overall error introduced by the approximation. Experimental results for 8-bit multipliers demonstrate that the proposed designs outperform the existing design in terms of power, achieving improvement of 15%. Furthermore, the proposed designs are evaluated using image processing and neural network applications.